Bump Technologies jobs - Palo Alto, CA
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| May 21 | Systems Infrastructure Developer | Cybercoders | San Francisco, CA |
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Youll make sure that when something goes bump in the night someone hears it And youll ... C++ etc Solid understanding of fundamental technologies like TCPIP HTTP Knowledge of... more |
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| May 18 | Product Engineer/Operations leader" | Cross Creek Systems | Cupertino, CA |
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I am currently looking for a Product Engineer/Operations leader. We have an outsourced model for Operations so this individual would need to be a senior engineer/manager that can... more |
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| May 18 | Lead Artist, Mobile Social Gaming | Filter | San Francisco, CA |
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of 3D lighting, and its effect on texture, bump, displacement mapping results. Excellent design skills, including the effective use of color, form, lighting and composition. more |
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| May 17 | I/O Planning EDA Applications Engineer | CAE Recruiters | San Jose, CA |
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teams. * Experience with packaging technologies like wirebond, SiP, interposers, and flip-chip including bump pattern development and RDL routing. * Knowledge of package layout... more |
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| May 15 | Sr. Package Design Engineer | ASE (U.S.) | Sunnyvale, CA |
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engineering test, wafer probe, wafer bump, substrate design and supply, wafer level package, flip chip, system-in-package, final test and design manufacturing services through... more |
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| May 15 | Sr. Packaging Application Engineer | ASE (U.S.) | Sunnyvale, CA |
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engineering test, wafer probe, wafer bump, substrate design and supply, wafer level package, flip chip, system-in-package, final test and design manufacturing services through... more |
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| May 15 | Packaging Engineer | Cisco Systems | San Jose, CA |
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accelerating manufacturing readiness of new technologies and new designs. * The candidate ... of bumping process with plating and printing technologies. * Strong background and... more |
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| May 14 | Senior Software Engineer | Oakland, CA | |
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Pandora Senior Software Engineer We have terrific opportunities in Software Engineering for innovative, inspired problem solvers who are enthusiastic about developing high-quality... more |
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| May 14 | Software Engineer- Web Developer | Oakland, CA | |
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code in Java. Knowledge of web view technologies such as JSP, Velocity. ... in Computer Science or a related field. Core Technologies HTML, CSS, Javascript, JQuery,... more |
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| May 12 | Packaging Design Integration Lead | Apple | Cupertino, CA |
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- Lead the evaluation of new package technologies considering trade-offs among electrical performance, power delivery, form factor, design rules, substrate and bumping technology,... more |
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| May 11 | Intern, Full Time | Marvell Technology Group | Santa Clara, CA |
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cost increases for chip production (Fab, Bump, Bumpsort, Sort, Die, Test, Assembly, etc). 11) Yield Database - update monthly yield database information which shows quarterly... more |
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| Apr 30 | Systems Infrastructure Developer | Yelp | San Francisco, CA |
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You'll make sure that when something goes bump in the night, someone hears it. And ... Solid understanding of fundamental technologies like TCP/IP, HTTP, Knowledge of best prac... more |
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| Apr 27 | Systems Infrastructure Developer - YP006 | Talent Merchants | San Francisco, CA |
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You'll make sure that when something goes bump in the night, someone hears it. And ... Solid understanding of fundamental technologies like TCP/IP, HTTP, Knowledge of best prac... more |
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| Apr 25 | Array Mixed-Signal Design Verification | Sunnyvale, CA | |
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Ready? Curiosity and fascination with new technologies and willingness to run toward a problem to be the one to solve it are the attributes that soar at this firm where innovation... more |
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| Apr 23 | SPMF-Scheduling Coordinator- EPIC | Sutter Health | San Francisco, CA |
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schedules, patient reminder reports, bump lists, and other scheduling support functions. Acts as a liaison with Sutter Physician Services regarding Epic-related issues. more |
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| Mar 22 | Senior Associate.Program Management. | Sapient | San Francisco, CA |
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Welcome to SapientNitro, where ideas reign supreme. Here, customer experiences are what drive us, game-changing marketing is conceived, awards are won, and technology is at the... more |
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| Mar 19 | Systems Infrastructure Dev | Cybercoders | South San Francisco, CA |
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You'll make sure that when something goes bump in the night, someone hears it. And ... - Solid understanding of fundamental technologies like TCP/IP, HTTP, - Knowledge of best p... more |
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| Mar 01 | Sr. Revenue Accountant | Xcel Group | Sunnyvale, CA |
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great, good work life balance and get a nice bump in pay. The ideal candidate will have previous experience with a software or technology clients, or experience working in a... more |
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| Feb 23 | Power Device Engineering - Sr Manager | Intersil | Milpitas, CA |
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and development of advanced Power Device Technologies (discrete and monolithic), ... advanced device structures and process technologies, the release to manufacturing of... more |
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| Feb 09 | Sr. Signal Integrity Engineer | Xilinx | San Jose, CA |
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co-simulation. 3). Flip-chip bump or wirebond padre-arrangement for chip-package-board co-design. 4). Optimal layer stackup &VDD/VSS plane/island assignment to minimize voltage... more |
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| Nov 22 | Hardware Developer 4 | Oracle | Santa Clara, CA |
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Name Semiconductor Package and PCB Technologies Department Description ... manufacturing, and qualification of new technologies for CPU and ASIC packages. The... more |
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| Nov 18 | SENIOR ENGINEER - IC PACKAGE DEVELOPMENT | NVIDIA | Santa Clara, CA |
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handheld products. Lead next generation bump and assembly technology development with ... flow, material set, design rules and fab/bump/assembly process controls needed to... more |
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| Nov 17 | Signal Integrity and Circuit Analysis Engineer | Xilinx | San Jose, CA |
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critical interfaces and I/O * Influence chip bump or wirebond pad location, based on any of the abovementioned analysis * Provide board/package guidelines including any of layout,... more |
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| Aug 02 | Signal and Power Integrity Engineer | Xilinx | San Jose, CA |
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Chip-package-board co-simulation. Flip-chip bump or wirebond pad re-arrangement for chip-package-board co-design. Optimal layer stackup & VDD/VSS plane/island assignment to... more |
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